Etched Silicon Wafers for Polishing
Etched Silicon Substrates
Most single side polished silicon wafers backside is etched. This means that the wafer's backside is not polished. The surface is rough. Etched is the step before polishing. The price of single side polished, back side etched wafer are less expensive than double side polished wafers all other specs being equal.
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Etching Silicon Wafer Terms
- Anisothopic etching
- Anisotropic etching
- Atching solution
- Etch process
- Metal etcher
- Chemical etching
- Ion etching
- Caustic etching
- Etching technique
- Silicon samples
- Silicon wafers
- Si wafers
- Bbuffered oxide
- Silicon nitride
- Etch rates
What are Etched Silicon Wafers?
Etched silicon wafers are thin disks made of silicon that have been chemically or mechanically processed to remove material and create patterns or structures on their surface. These patterns or structures can be used to create microelectronic devices such as transistors, capacitors, and resistors, which are the building blocks of electronic circuits.
Silicon wafers are typically used as the substrate, or base material, for microelectronic devices because silicon is a good electrical conductor and has a stable crystal structure that is conducive to the creation of precise and reproducible microstructures. To create etched silicon wafers, manufacturers first start with a flat, polished silicon wafer. They then use a variety of techniques to remove material from the surface of the wafer in a controlled manner, such as chemical etching or laser ablation. The resulting wafer will have patterns or structures etched into its surface that can be used to create microelectronic devices.
Etched Silicon Wafer Going into Polisher
Etched Silicon Substrates Inventory
Below is just some of the etched silicon wafers that we have in stock.
| Item | Type/Dopant | Orien | Diam (mm) |
Thck (μm) |
POL | Res Ωcm | Specs |
|---|---|---|---|---|---|---|---|
| N445 | n-type Si:P | [112-5.0° towards[11-1]] ±0.5° | 6" | 875 ±10 | E/E | FZ >3,000 | SEMI, 1Flat (47.5mm), TTV<4μm, Surface Chips |
| S5622 | n-type Si:P | [100] | 6" | 1,300 ±10 | E/E | FZ 0.01-0.05 | SEMI notch, Empak cst |
| J668 | P/B | [111] ±0.5° | 6" | 675 | E/E | 0.010-0.025 | SEMI, 1Flat (57.5mm), Empak cst, TTV<5μm |
| 5814 | n-type Si:P | [100] | 6" | 925 ±15 | E/E | 5-35 {12.5-29.7} | JEIDA Prime, Empak cst, TTV<5μm |
| S5614 | P/B | [100] | 5" | 635 ±15 | E/E | FZ >5,000 | 2Flats, Empak cst |
| 5744 | P/B | [100] | 5" | 920 ±10 | E/E | FZ >1,000 | 2Flats, Empak cst |
| S5802 | P/B | [100] | 5" | 600 ±10 | E/E | 2.0-3.5 | SEMI, 1Flat, coin roll |
| X7135 | P/B | [100] | 5" | 710 | E/E | SEMI Test, 1Flat, Empak cst | |
| 7188 | n-type Si:As | [111] | 5" | 625 | E/E | 0.001-0.005 | 1Flat, Empak cst |
| X7134 | n-type Si:As | [100] | 5" | E/E | 0.001-0.005 | SEMI Test, 1Flat, in opened Empak cst | |
| X7167 | n-type Si:Sb | [100] | 5" | 740 | E/E | SEMI 2Flats (2nd @135°), in opened Empak cst, 125.63mm diameter | |
| S5798 | n-type Si:P | [100] | 4" | 915 ±10 | E/E | FZ 2,000-3,000 | 1Flat at [100], Empak cst |
| B987 | n-type Si:P | [112-5° towards[11-1]] ±0.5° | 4" | 795 | E/E | FZ >100 | SEMI, 1Flat, in Empak, TTV<4μm, Lifetime>2,000μs |
| 5618 | n-type Si:P | [100] | 4" | 737 ±12 | E/E | FZ 8.8-11.2 | SEMI, 2Flats, Empak cst |
| 2932 | n-type Si:P | [111] ±0.5° | 4" | 500 ±13 | E/E | FZ 6.03-7.37 | SEMI, 2Flats |
| TS035 | P/B | [110] ±0.2° | 4" | 605 ±10 | E/E | 30-60 {33-41} | Ready-to-polish, 2 SEMI Flats: PF@<111>±0.2°, SF @ <111> 109.5° CW from PF, TTV<2μm, in coin-roll between tissues |
| S7780 | P/B | [100] | 4" | 350 | E/E | 7-14 | SEMI Prime, 2Flats, Empak cst |
| S7797 | P/B | [100] | 4" | 350 ±5 | E/E | 7-14 | SEMI Prime, 2Flats, Empak cst, cannot be polished |
| S5841 | P/B | [100-0.5°] | 4" | 590 ±10 | E/E | 1-3 | SEMI Prime, 2Flats |
| S5870 | P/B | [100-0.5°] | 4" | 575 ±10 | E/E | 1-10 | SEMI Prime, 2Flats, Empak cst |
| E408 | P/B | [100] | 4" | 600 | E/E | 1-100 | SEMI Test, 1Flat, Empak cst, No Edge-Rounding |
| 6838 | P/B | [100] | 4" | 545 ±10 | E/E | 1-10 | SEMI Prime, 2Flats, Empak cst |
| 7221 | P/B | [100] | 4" | 560 ±10 | E/E | 1-10 | SEMI Prime, 2Flats |
| 5833 | P/B | [100] | 4" | 300 | E/E | 0.01-0.02 | SEMI Prime, 2Flats, Empak cst, TTV<4μm |
| S5763 | n-type Si:P | [100] ±1° | 4" | 465 ±10 | E/E | 1-3 | SEMI, 1Flat, Empak cst |
Common Etching Processes for Silicon Wafers
The etching process reduces the silicon layer to a n-dimensional structure by chemically dissolving the silicon layer in an acidic solution. The sample is then heated to a specific molten point and is then subjected to a series of tests to evaluate the etching rate, uniformity, and mask selectivity. Here are some common etching processes that are commonly used in semiconductor manufacturing.
Before contacting the etchant, the wafer's surface roughness is reduced by more than 50%. The variation in total thickness prior to the etching process was at least 20 microns; after the etching process, the total thickness variation was less than three microns. The etched silicon wafer's edge portion is located between the nearest peripheral edge point and the central axis, extending between one and fifteen millimeters from the edge point.
After the etchant is applied, the front and back surfaces of the etched silicon wafers are inspected. In general, the front and back surfaces of the resulting etched silicon wafers have average surface roughness of 1.5-microns. However, the GBIR method is not a suitable method for the front surface, as it causes unevenness. In order to improve the etching process, the front and back surfaces of the etchant should be flat and the thickness should not exceed 20 microns.
The etchant is applied to the edge of the etchant-etched silicon wafer before it is contacted with an etchant. This procedure aims to relieve stress within the silicon wafer and avoid bowing. Typically, 0.5 to two microns are removed from the back and front surfaces. The final surface roughness should be less than 1.5 mm. Once the etchant has been applied, the etched silicon is ready to be fabricated.
When a portion of the front surface of an etched silicon wafer is etched, it is typically at least 0.3 mm Ra. The surface roughness is usually less than two microns. This is the limiting plane in wet chemical etching of the silicon layer. In addition, the 111 plane is the limiting plane in wet chemical methods of etching. If the 111 plane is etched, it will typically exhibit a surface roughness of less than 1.5 mm.
A part of an etched silicon wafer is exposed to an etchant before the etching process begins. This etchant reduces the total thickness variation of the wafer by about 3 microns. The etchant is applied to the front and back surfaces of the silicon. It is not used for manufacturing cellular electronics. It is used for manufacturing conductive and semiconducting materials.
Using this process, silicon wafers are exposed to a solution of acidic chemicals that removes the oxide layers on the surface. This results in a thin layer of silicon nitride. The acid and water solutions are heated to an optimum temperature for the etching process. A high pH balance prevents an explosive reaction. The chemical etchant is applied to the back and front surfaces of a silicon wafer.
An etching process is used to remove unwanted material from silicon wafers. The process involves applying a liquid solution to a wafer and rotating it to continuously contact the edge. It can be anisotropic or etchant-coated. In general, the etching process is done to remove a small amount of silicon from a silicon wafer. Aside from the advantages of an etchant, it is important to note that the etching process requires more time and money to complete.
When a silicon wafer is etched, a thin film of silicon nitride is deposited directly onto the silicon. In this process, a thin film of silicon niride is deposited directly on the surface of the silicon wafer. After the etching process is complete, the phosphoric acid and water are added to the nitride bath. The nitride bath is a temperature-controlled environment, and it is crucial to avoid adding too much water or the acid can cause a dangerous explosion.
The edge of silicon wafers is a crucial area for etching. This process allows the wafer to be more precise. Despite its low-tech nature, etching is a very complex operation that requires specialized equipment. To prevent this, many different etching methods are used in semiconductor manufacturing. In addition, a specialized process is used for developing semiconductor devices. Once the silicon is etched, the edges must be cleaned.