Lapped Silicon Wafers to Fix the Wafer's Surface Damage
Why Use Lapped Wafers?
Scientists Requested the Following:
We would like to ask you about the possibility of providing diffused silicon wafers, with a typical phosphorous diffusion for the fabrication of solar photovoltaic cells. More specifically, we would need P type (boron doped) silicon wafers with a phosphorous diffusion to obtain a sheet resistance of about 110 ohm/square. Regarding the wafers, we are interested in one-side polished wafers (<1-0-0>; 150 mm of diameter; 675 microns of thickness). I think your wafers fulfill these specifications. Also, we would like to ask if you are able to provide typical wafers used for the fabrication of solar cells (about 156x156 mm semisquare non-polished wafers; about 170 microns of thickness; P-type with the same phosphorous diffusion.
UniversityWafer, Inc. Quoted
156mm x 156mm N/Ph [100]±3° 150 ±10um Lapped 1-7 ohm-cm Pseudo-Square PV, MCC Lifetime>1,300μs
Reference #264504 for pricing.
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Silicon Wafer Lapping Process
The lapping of Silicon Wafers is a process that has been around as long has substrates needed a very flat and polished surface. The lapping techinique is to this day the best machining process that gives the silicon substrate a higher quality finish that are characterized by isotropic properties.
What is Lapped Silicon Wafers
Using Lapped Silicon Wafers to test the cleanliness and surface quality of a silicon chip is one of the least expensive methods. It matches the precision of the surface of a silicon wafer. UniversityWafer, Inc. provides lapping services for small to large diameter silicon wafers in small and large volumes.
UniversityWafer, Inc. and parterns, lapping services removes rough impurities to smooth and make uniform the silicon wafer's surface. The lapping process can achieve thickness tolerances as close as 0.00254mm.
Lapped silicon wafers will be several millimeters thick. Oxidizing the wafers removes impurities in less than one minute. The amount of time the silicon wafer is oxidized in this batch usually equals the width of the silicon wafer.
Lapped Silicon Wafers
After slicing the ingot there is usually a mechanical double side polished lapping step to remove damage left by slicing to achieve a high degree of parallelism and flatness of the wafer. Lapping performed under rotational pressure with pads and an abrasive slurry mixture that typically consists of alumina or silicon carbide and glycerine. Flatness is a critall wafer parameter for many process steps in the wafer fabrication process.
A polished wafer edge finish (also called ege grind) is applied to the wafer to contour a smooth radius on the edge of the wafer create mechanical stress in the wafer that activates crystal dislocations, especially during thermal process steps that occur in the wafer fabrication. Crevices can also be the source of unwanted contamination buildup as well as particulate flaking during fabrciation. A smooth edge readius is important to minimize these concerns. Futhermore, chipped edges are a source of edge dislocation growth during thermal cycles in the wafer fabrication process.
UniversityWafer, Inc. uses a polishing pad along with polishing liquid to to remove excess silicon from a wafer surface. The reason for Lapping process is to de-stress the ingot during slicing. Lapping also removes defects on the both sides of the wafer's surface.
Below are just some of the Lapped Silicon Wafers that we have in stock.
| Item # | Type/Dopant | Orient. | Dia(mm) | Thick(μm) | Polish | Res Ωcm | Notes |
| 2533 | n-type Si:As | [100] | 6" | 1,000 | L/L | 0.0033-0.0037 | SEMI, 1Flat(57.5mm), in individual wafer cassettes |
| E533 | n-type Si:As | [100] | 6" | 1,000 | L/L | 0.0033-0.0037 | SEMI, 1Flat(57.5mm), in individual wafer cassettes |
| 7201 | n-type Si:P | [100] ±3° | 156x156 | 150 ±10 | L/L | 1--7 | PSQ (Pseudo-Square), PV, Coin-roll packed |
| E189 | n-type Si:P | [100] | 4" | 300 | L/L | FZ 1,100-1,600 | SEMI, 1Flat, Empak cst |
| D189 | n-type Si:P | [100] | 4" | 300 | L/L | FZ 800-1,500 | SEMI, 1Flat, Empak cst |
| H189 | n-type Si:P | [100] | 4" | 300 | L/L | FZ 800-1,500 | SEMI, 1Flat, Empak cst |
| X7299 | n-type Si:As | [111-4°] | 4" | 525 | L/L | SEMI TEST (in Opened Empak cst), 2Flats (2nd @ 45°) | |
| D10 | n-type Si:P | [111] | 2" | 400 | L/L | 120-170 | Lapped & edged |
Lapped Meaning
What does lapped wafers mean? This term refers to a silicon chip that is smooth and uniform on its surface. A lapped wafer is typically one that has been processed to eliminate imperfections. This process results in an oxide layer on the wafer's surface that is 1.5 to 2.0 microns thick. It also ensures that the finished product has a uniform dimensional property. This process is ideal for high-speed processing because the wafer is free of work damage and metallic particles.
In the production of LED chips, wafers are made from ingots, which are solidified crystal growths. Diamond saws are used to separate individual wafers, and these are then polished and lapped to form an array of individual chips. The purity of crystal and the lattice structure are critical to the quality of a wafer. The lapping process removes surface defects. However, the process is not perfect.
To produce the most refined semiconductors, semiconductor manufacturers use a process called lapping. This technique is used to remove rough impurities from silicon wafers. The lapping process is a mechanical process that removes rough surface elements from silicon wafers. The end result is a smooth surface that is several millimeters thick. This process is often performed after the silicon wafer has been sliced.
Lapping Silicon Wafers
This article presents a technique for lapping silicon wafers, using a Lapping surface plate. This plate has a surface hardness of 430 Hv, a spheroidization percentage of graphite, and a slurry distribution hole 52. Here are the main benefits and limitations of this method. We also discuss the application of this process to silicon lithography and semiconductor fabrication. This is an important step in the process of silicon lithography and reprocessing.
Lapping surface plate 1 can be utilized for lapping silicon wafers
A high-hardness lapping surface plate is fabricated with a material that is controlled for hardness. The matrix structure of a cast iron base material is hardened. Specifically, an 8-inch silicon wafer was lapped with a lapping surface plate of #1200. The result was equivalent flatness and scratch occurrence. The lapping surface plate is not inferior to a conventional lapping surface plate, and the thickness tends to increase with silicon wafer diameter.
The shape and composition of the lapping surface plate is similar to that of example 1. Table 1 shows the composition of the cast iron. This material contains 2.0 wt % carbon, which crystallizes into spheroidal graphite. Coarse carbide particles of 20 mm and greater do not precipitate because graphitization accelerating elements, such as Si, Ni, and Cr, are present in the alloy.
The abrasive particles that fall from the traditional metal lapping plate result in uneven stress distribution, which results in a poor surface roughness value. In contrast, the self-sharpening lapping surface plate is highly effective in removing material with the least amount of surface roughness. If you are interested in lapping silicon wafers, this method may be suitable for you.
It has a surface hardness of 430 Hv
The lapping operation flattens the surface of semiconductor substrates, such as silicon wafers. This process also applies to the surface of jewels, metals, and ceramics. As semiconductor substrates have become more flat and integrated, maintaining the flatness of their surface plate has become more important. This article will review a few of the common reasons why lapping is important.
A surface plate used for lapping silicon wafers can be made from material with a high hardness. The matrix structure of cast iron base material can be hardened. In the example of a silicon wafer, the surface plate has an outside diameter of about 8 inches and is 203 mm thick. The thickness of a lapping plate is typically 40 to 60 mm.
A lapping surface plate with a surface hardness of 450 Hv was produced by quenching and tempering cast iron. The material was then cooled to room temperature by air. Its hardness increased to 550 Hv after secondary hardening. While the surface hardness of silicon wafers is 430 Hv, its surface hardness is higher than that of silicon.
The process of lapping silicon requires a selection of abrasive media, machine parameters, and processing times. A hard metal plate and a free abrasive can efficiently remove a few hundred microns of material. The lapping time required to remove a few hundred microns of material ranged from ten to twenty minutes. When silicon carbide paper was used, it failed to remove lapping damage, mechanical damage, or pitting.
It has a spheroidization percentage of graphite
Graphite crystallizes at different rates in various materials. Graphite has several different structures: spheroidal, flake, eutectic, and eutectic-flake. For lapping silicon wafers, the preferred structure is spheroidal graphite with a spheroidization percentage of 70% or higher.
A lapping surface plate can achieve high hardness by using a material that possesses a spheroidization percentage. A material with a high spheroidization percentage can be controlled to achieve a uniform hardness. For example, a large lapping surface plate made of graphite can achieve a uniform hardness while restraining deformation.
A spheroidization percentage of graphitic graphite is the most common spheroidization property. This characteristic is important for the fabrication of advanced devices that have high accuracy. Lapping silicon wafers with high spheroidization percentage will increase the efficiency of semiconductor manufacturing. This type of surface polishing is also effective for precision measurements.
It has a slurry distribution hole 52
Slurry passages on lapping silicon wafers are circular and vary in width based on the polishing process. The width and depth are proportionate to the gap between the wafer and the retainer ring. The circular path allows slurry to circulate within the retainer ring and distribute it evenly over the entire surface of the wafer. This design enables the slurry to reach all facets of the wafer, including the edge portions.
Slurry passages 52 provide an even distribution of slurry over the entire surface of a silicon wafer. The slurry passages 42 are generally straight grooves, and the retainer ring spins counterclockwise. Persons skilled in the art may rearrange the grooves to rotate the retainer ring clockwise. Each slurry passage is approximately 0.050.3 mm wide and 24 mm deep.
In addition, the slurry distribution hole 52 should be large enough to cover all the silicon surface area, and should not be too small. The slurry distribution hole is an essential component of the process and should be placed centrally to ensure uniform distribution. It should be located centrally to avoid the possibility of slurry spewed into other areas. Once the slurry is distributed, it should flow smoothly through the wafer.
A conventional CMP machine is inefficient and unevenly distributes the slurry. Using a CMP system with a retainer ring evenly distributes the slurry on the wafer surface. A circular path allows the slurry to flow evenly over the entire wafer surface. It achieves a uniform planar surface. It is also more efficient than a conventional CMP machine.
It requires quenching or rapid cooling
For the lapping process, a metal object must be cooled quickly in an appropriate medium. There are many types of quenching processes, including interrupted quenching, interrupted rapid cooling, and slow-speed quenching. Generally, the process involves a rapid cooling of a metal object at a temperature above its quench medium. The following are a few examples of quenching methods:
It removes saw marks and other surface defects
The lapping process involves removing saw marks and other surface defects on silicon wafers. It also thins the wafer to reduce stress from the slicing process. During this process, the wafers are cleaned and etched using acetic and sodium hydroxides to eliminate microscopic cracks. Afterwards, they go through a critical edge grinding process to round off the edges and reduce breakage during subsequent manufacturing processes.
To remove saw marks and other surface defects, the silicon wafer is first exposed to a diamond saw wire that laps the surface. The sawwire moves through the silicon wafer while grinding agents are running along the rotating wire. The process removes saw marks while maintaining the high cutting capability of the diamond saw wire. In addition, the resulting formed surface can be used for conventional wet acid etching.
During the process of lapping silicon wafers, large abrasives and other particles are discharged and are not removed in a short time. The resulting direct dry friction damages the machined surface. To reduce the adverse mechanical effects of abrasives, the yield effect can be utilized. In addition, the yield effect can help reduce the amount of material removed by reducing the rate of surface defects. Hence, it is necessary to balance the choice of lapping disc material with the technological purpose.